1. Field of Invention
The present invention relates to a structure of a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a structure of a non-volatile memory capable of preventing the antenna effect and the fabrication thereof.
2. Description of Related Art
In a method for fabricating a non-volatile memory, a charge trapping layer and a polysilicon gate are formed sequentially on a substrate and then a source/drain region is formed in the substrate beside the polysilicon gate. When the charge trapping layer is a silicon nitride-based layer, the non-volatile memory can be called a xe2x80x9cnitride read-only memory (NROM)xe2x80x9d.
In a process of fabricating a non-volatile memory with a charge trapping layer, plasma techniques are frequently used. However, when a transient charge unbalance occurs in the plasma, charges will move along the conductive portions on the target wafer. Such an effect is called the xe2x80x9cantenna effectxe2x80x9d. Consequently, some charges are injected into the charge trapping layers of the non-volatile memory to unevenly raise the threshold voltages (VT) of the memory cells, i.e., to produce a programming effect. Therefore, the VT distribution of the non-volatile memory is much broadened, being usually from 0.3V to 0.9V.
In order to prevent the programming effect caused by the antenna effect, a diode is formed in the substrate to electrically connect with the word-line in the prior art. When the charges accumulated on the word-line reach a certain amount to produce a voltage higher than the breakdown voltage of the diode, the charges are released in a breakdown manner. However, the programming effect cannot be completely eliminated with this method since there may still be some charges injected into the charge trapping layer even if the voltage produced is lower than the breakdown voltage of the diode. Moreover, by using this method, the input voltage of the non-volatile memory is lowered by the diode to adversely decrease the operating speed of the memory device.
Accordingly, this invention provides a non-volatile memory and the fabrication thereof to prevent the charge trapping layer of a non-volatile memory from being damaged in a plasma process.
This invention also provides a non-volatile memory and the fabrication thereof to prevent the non-volatile memory from being programmed in a plasma process, so that the threshold voltages (VT) of the memory cells are not raised and the VT distribution is not broadened.
This invention also provides a non-volatile memory and the fabrication thereof to avoid the input voltage of the memory device from being lowered, so that the operating speed is not decreased.
The non-volatile memory of this invention includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion of the word-line is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate. The high resistance portion of the word-line is, for example, narrower than the other portions of the word-line in order to have a higher resistance.
This invention also provides a method for fabricating a non-volatile memory capable of preventing the antenna effect. In this method, a charge trapping layer is formed on a substrate and then a word-line having a high resistance portion and a memory cell portion is formed on the substrate. A grounding doped region is formed in the substrate and then the high resistance portion of the word-line is electrically connected with the grounding doped region. Thereafter, a metal interconnect is formed over the substrate to electrically connect with the memory cell portion of the word-line. When the process is completed, a large current is applied to blow the high resistance portion of the word-line.
This invention provides another method for fabricating a non-volatile memory capable of preventing the antenna effect. A charge trapping layer, a polysilicon layer and a metal silicide layer are formed sequentially on a substrate and then patterned to form a word-line having a memory cell portion and a high resistance portion. A grounding doped region is formed in the substrate and then a first contact is formed on the substrate to electrically connect the grounding doped region and the high resistance portion of the word-line. A second contact is formed over the substrate to electrically connect with the memory cell portion of the word-line. When the process is completed, a large current is applied to blow the high resistance portion of the word-line.
Because this invention uses a high resistance portion of the word-line to conduct the charges accumulated on the word-line into the substrate in a plasma process, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random. Moreover, since the high resistance portion of the word-line has a high resistance, applying a large current can easily blow the high resistance portion to disconnect the word-line from the grounding doped region after the manufacturing process. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.